Investigating runtime task mapping for NoC-based multiprocessor SoCs

Abstract

Multiprocessor Systems on Chip (MPSoCs) are a trend in VLSI design, since they minimize the design crisis configured by the gap between the silicon technology and the actual SoC design capacity. An important issue in MPSoCs is task mapping. Applications running in MPSoCs execute a varying number of tasks simultaneously, where each task may be started at some distinct moment, according to applications requests. Thus, task mapping should be executed at runtime. This work investigates the performance of dynamic task mapping heuristics in NoC-base MPSoCs, targeting NoC congestion minimization. Tasks are mapped on demand, according to the NoC channels load. Results using congestion-aware mapping heuristics compared to a straightforwardly defined heuristic achieve better results. In average, it is possible to reach up to 31% smaller channel load, up to 22% smaller packet latency, and up to 88% less.