Abstract
This paper investigates the origin of the fixed positive oxide charge often experimentally observed in Metal Oxide Semiconductor (MOS) structures of SiO2 formed on cubic silicon carbide (3C-SiC). The electrical properties of MOS structures including either thermally grown SiO2 or deposited SiO2 by Plasma Enhanced Chemical Vapour Deposition (PECVD) on epitaxial 3C-SiC layers grown directly on Si are investigated. MOS structures with a range of oxide thickness values subjected to different thermal treatments were studied. It was found that both thermally grown and deposited SiO2 on 3C-SiC exhibit similar positive charge levels indicating that the charge originates from interface states at the 3C-SiC surface and not from the oxide. The nature of this surface charge in the SiO2/3C-SiC system is also discussed based on the current data and previously published results.
Highlights
SiC presents a high electric breakdown field and a wide band gap which makes it a suitable semiconductor for power electronics.[1]
An example of multi-frequency capacitance voltage (C-V) characteristics measured on an Al/SiO2/3C-SiC/Si Metal Oxide Semiconductor (MOS) structure is shown in figure 1
The level of positive charge detected in this study suggests that the acceptor band possibly extends more than 1.4eV above the valence band edge and/or large C clusters are present at the interface and generate a band of acceptor levels higher in the band gap which is intersected by the surface Fermi level
Summary
SiC presents a high electric breakdown field and a wide band gap which makes it a suitable semiconductor for power electronics.[1] The hexagonal SiC polytype (4H-SiC) is by far the most studied SiC polytype[2] and currently large bulk wafers of 4H-SiC are commercially available, albeit at a much larger cost than typical Si wafers used in the microelectronics industry.3 3C-SiC presents a significant cost advantage over 4H-SiC as it can be grown directly on Si by Chemical Vapour Epitaxy (CVD) at high temperature.[4] The availability of good quality 3C-SiC epitaxial layers on Si will enable the implementation of cost effective SiC power devices in the range 650V to 1200V. The presence of oxide charge could shift the transistor characteristics or could affect the electric field profiles at the device edge terminations or in extreme cases could generate unwanted inversion layers at the oxide/SiC interface resulting in high levels of junction leakage currents. The work describes the characterisation of various gate oxide layers grown on the n-type drift layer, rather than a p-type body, to simplify and focus the problem on the SiO2/SiC interface
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