Abstract
Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high-k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the ION/IOFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V/V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates.
Highlights
Nowadays, innovative products exploring the flexibility and the transparency of modern semiconducting materials are reaching the market maturity
Different scientific groups and companies are focused on the advancement of this technology, in which thin-film transistors (TFTs) are essential elements being responsible for driving the currents in the system [1,2,3]
The transistor geometry and the choice of the used materials have a crucial impact on the field of possible applications either for analog or digital circuits
Summary
Innovative products exploring the flexibility and the transparency of modern semiconducting materials are reaching the market maturity. In contrast to the appreciated low annealing temperature processes the large surface area of the used nanoparticles increases the interaction with the ambient This interaction is reported to induce instabilities to the electrical characteristics of the transistor if a passivation layer or a stabilization step is not applied [11,12,13]. In order to avoid the chemical and physical stress suffered by the semiconducting layer, several groups make use of shadow masks instead of conventional lithography technique This method prevents the integration of high density circuits, limits the minimum transistor size to about 10 μm, and it is not entirely suitable for large area substrates. As low temperature processes (maximum temperature of 115 ◦C) are used, no sintering
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