Abstract
We have designed an all-optical NOT gate on SOI with a footprint of 1.2×1.2 μm2. The device designed by a PSO method and simulated by FDTD. The overall response time is < 2 ps.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.