Inverse Sine Phase Detector Phase Locked Loop Associated with Modified Multi Band LC Quadrature Voltage Controlled Oscillator for Wireless Communication Systems at 0.9, 1.8, 2.4, 3.5 GHz

Mahmoud Abdellaoui

doi:10.3844/ajeassp.2009.328.336

Abstract

Problem statement: In this study and in consequence of the restricted performance of the multi standard wireless receiver utilizing the classical architectures, we proposed and presented a new architecture of multi band wireless receiver based on an Inverse Sine Phase Detector Phase Locked Loop (ISPDPLL) associated with modified multi band LC quadrature Voltage Controlled Oscillator (VCO), supporting GSM/DCS/DECT/Bluetooth/WiMax systems. Approach: To accomplish the multi standard receiving architecture at sufficiently good performance and at a low hardware cost, the proposed circuit, using an ISPDPLL associated with VCO based on switched capacitors utilizing a several numeric controlled capacitive branch and cross-coupled transistors, was implemented in 0.35 μm CMOS technology and designed to yield quadrature output signals (I-Q) allowing to eliminate the dephasing block (90°) employed in a multi band Zero IF architecture receiver, that make the proposed architecture amenable for monolithic integration and 4G multi standard application. Results: This novel system presented high performance and good potentiality to cover perfectly the wireless multi standard receiving on the large band with the same transmission condition. Conclusion/Recommendations: The performance of this system was analyzed and demonstrated to have a minimum phase noise, a good Factor Of Merit (FOM) and wide tuning for these standard applications.

Highlights

Phase Locked Loop (PLL) is used widely in the implementation of modern systems, in the field of communication applications
The Inverse Sine Phase Detector Phase Locked Loop (ISPDPLL) is a PLL structure without using any filters and the phase detector and the loop filter used generally in the standard PLL are replaced by a Inverse Sine Phase Detector (ISPD) including a track and Hold circuits (T/H), an inverse converter and a Voltage Controlled Oscillator (VCO)[2,3,4]
We presented and described a detailed of the design of the novel synthesizer based on ISPDPLL associated with a modified multi band LC quadrature VCO to insist on an originality of the system and his performance

Summary

Introduction

Phase Locked Loop (PLL) is used widely in the implementation of modern systems, in the field of communication applications This PLL, called classical PLL, presents many disadvantages and limitations due especially by the loop filter which causes many problems such as aliasing effect and the limitation of bandwidth because if the filter bandwidth is decreased, the capture process became slower, the capture range decreases and the lock up time increases. Many studies are developed to reduce phase error and phase noise by the addition of feedback loops[1] In this way, the standard PLL can be tuned by first designing the transient and steady state of a second-order PLL and taking care of the working operation under steady frequency (third order) and frequency ramps (fourth order). To accomplish the multi band receiving architecture (Fig. 1) at a low hardware cost, many propositions are presented based on:

Objectives

Methods

Results

Conclusion