Abstract
In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-optimized mask was generated for each designated illumination condition as the source was swept through various parameter settings in order to find the best combination of source and mask. This approach has been successfully applied to explore and select lithography processes and design rules for advanced semiconductor technology nodes. In Luminescent's latest implimentation of ILT-enabled SMO, the same Level Set Method used in the mask optimization is used in the source optimization; in other words, the source map is represented by a level set function. During the optimization process, the level set function evolves to achieve a minimized cost function, where the cost function is defined as the difference between aerial image and ideal image (MEEF and DOF can also be used in the cost function) via a gradient flow, and the gradient flow is based on the cost function itself. This flow is interlaceded with the mask inversion flow so that a simultaneous mask & source co-optimization is achieved. In this paper a number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of ILT-enabled SMO.
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