Inverse Design for Low Warpage Ultra-Thin Packages Using Constrained Particle Swarm Optimization

Cheryl Selvanayagam,Brett Wilkerson,Pham Luu Trung Duong,Nagarajan Raghavan

doi:10.1109/access.2021.3072128

Abstract

Warpage of electronic packages is the result of mismatch in the coefficient of thermal expansion (CTE) between the silicon die (CTE = 2.6ppm/°C) and the substrate (CTE = 15–25 ppm/°C). In ultra-thin packages, the reduced thicknesses can result in even higher package warpage due to the reduced flexural rigidity. Current approaches to minimize warpage include selecting constituent materials in the substrate with lower CTE as well as carrying out copper balancing of metal layers which are equidistant but on opposite sides of the core. In this work, we aim to optimize the metal density of the substrate layers by using an inverse design framework using Particle Swarm Optimization (PSO) with carefully selected constraints to minimize the rework required on the electrical tracing artwork. Results show that the inverse design framework is able to arrive at a 20% reduced warpage by changing local metal densities by just up to 5%. This is a significant reduction in warpage that is achievable by incorporating minor changes to the electrical artwork of the substrate. In future, this methodology can be applied to not only minimize warpage on ultra-thin packages but also enable even thinner ultra-thin package designs to be realized.

Highlights

As packages and silicon dies grow to allow for greater functionality and performance while decreasing in thickness to accommodate the dimensions of the final product they go into, we are fast approaching the limits of the design rules
Three case studies with the optimization were carried out with different constraints such that the objective of reducing the current warpage profile by 20% can be achieved, in a manner that can be translated to the electrical design of the substrate
We have shown that accurate inferences about substrate subsection coefficient of thermal expansion (CTE) can be made by incorporating an finite element analysis (FEA) model with Markov Chain Monte Carlo (MCMC)

Summary

Introduction

As packages and silicon dies grow to allow for greater functionality and performance while decreasing in thickness to accommodate the dimensions of the final product they go into, we are fast approaching the limits of the design rules. In order to break free from these constraints, new design methodologies are presently required. Concepts such as inverse design and optimization are key to unlocking better electronic designs in the near future, especially for AI-enabled edge computing applications as well as for 3D integrated circuits requiring heterogeneous integration. Image Correlation (DIC) to realize a more optimum design in terms of the overall warpage of the package. Once this framework is established, we use the existing and target warpage profiles and current metal densities as inputs to the optimization routine to determine the locations on the substrate where the metal density should change and by how much in order to approach the target warpage profile. The change in metal density at every location was constrained to change within ±5% of the original design and in the third one, a decrease in metal density of up to 30% was used to constrain the optimization

Objectives

Results

Conclusion