Introduction

Abstract

During the course of the design process, a number of high-level decisions are typically made. For example, consider the design of an analog-to-digital converter. There are several options for the conversion algorithm, such as flash, successive approximation, dual slope integration, switch capacitor, etc. Once the conversion algorithm is selected, the logic and circuit design of the various computational units (e.g., counters, encoders, comparators, etc.) must be performed. Again, there are design decisions. Looking at a counter, there are several approaches to realizing the next state decoder and memory (e.g., RS flip-flop, JK flip-flop, etc.). In addition, a wide variety of fabrication technologies are available, such as CMOS (complementary metal-oxide semiconductor), STTL (Schottky transistor transistor logic), ECL (emitter-coupled logic), etc. These high-level decisions have a substantial impact on the performance of the finished product. Taken collectively, we call these decisions the design plan. In general, there can be an extremely large number of design plans that could yield designs that satisfied a set of initial functional specifications, but with greatly varying performance in terms of area, power dissipation, etc. Thus, each design plan results in a design that has a different set of tradeoffs.