Abstract
Two papers were selected from the digital hardware related sessions of ISSCC 2019. Both papers propose energy-efficient architectures and circuits for accelerating deep neural networks inference and training. The first paper, by Kim et al. , demonstrates a mobile processor that can perform reinforcement learning at high energy efficiency (2.1 TFLOPS/W) via a novel experience compression scheme. The second paper, by Lee et al. , proposes another energy-efficient processor for learning. It can flexibly support 8-bit floating point (FP8) to 16-bit floating point (FP16) and achieves 25.3 TFLOPS/W.
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