Abstract
A new structure to develop 64-bit RSA encryption engine on FPGA is being presented in this paper that can be used as a standard device in the secured communication system. The RSA algorithm has three parts i.e. key generation, encryption and decryption. This procedure also requires random generation of prime numbers, therefore, we are proposing an efficient fast Primality testing algorithm to meet the requirement for generating the key in RSA algorithm. We use right-to-left-binary method for the exponent calculation. This reduces the number of cycles enhancing the performance of the system and reducing the area usage of the FPGA. These blocks are coded in Verilog and are synthesized and simulated in Xilinx 13.2 design suit.
Highlights
It is very important in today‟s world to develop new ways to guarantee their security as far as the data communication is concerned
The main problem is the selection of the key privately. In asymmetric cryptography this problem is overcome by using an algorithm that deals with two keys
The problem discussed in many ways [12][13][14]. [12] has provided the high speed RSA implementation of FPGA platforms, [13] showed the high speed RSA implementation of a public key block cipher-MQQ for FPGA platforms, [14] has provided the implementation of RSA algorithm on FPGA
Summary
It is very important in today‟s world to develop new ways to guarantee their security as far as the data communication is concerned. The idea behind publishing one key (the public key) and keeping the other one secret (the private key) can surely make the whole procedure more secure and protected. Those will be able to read the message who may have the private key as well, if someone wants to encrypt the message it is necessary to have both keys [2]. For RSA implementation the most important step is to select the prime number, in this paper we are proposing a fast Primality testing algorithm that supports in generating the key which is the first step of RSA algorithm [15]. The work presented in this paper implements the modular exponentiation operation by simple right-to-left-binary method, which helps to reduce the processing time
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