Intrinsic Vulnerability to Soft Errors and a Mitigation Technique by Layout Optimization on DICE Flip Flops in a 65-nm Bulk Process

Abstract

We found that specific pairs of pMOS and nMOS transistors in dual interlocked storage cell flip flop (DICEFF) become sensitive to soft errors by device simulations. We propose several layout structures that can improve soft-error tolerance with additional 39%-46% area overhead. We evaluated soft-error tolerance of a D-type FF (DFF) and DICEFFs in a 65-nm bulk process by heavy ions. Our experimental results showed that the DICEFF has more than 300× better soft-error tolerance than the DFF by Kr (LET 40.3 MeV·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg) irradiation when the supply voltage is 1.2 V, and the DICEFF has only 9× better soft-error tolerance than the DFF when the supply voltage is 0.6 V. However, the proposed DICEFF with 46% area overhead has 58× better soft-error tolerance than the DFF when the supply voltage is 0.6 V. DICEFF has so many sensitive pairs and lower soft-error tolerance as supply voltage decreases that cannot be applied to highly scaled process technologies.