Intrinsic evolvable hardware platform for digital circuit design and repair using genetic algorithms

Abstract

A hardware/software platform for intrinsic evolvable hardware is designed and evaluated for digital circuit design and repair on Xilinx Field Programmable Gate Arrays (FPGAs). Dynamic bitstream compilation for mutation and crossover operators is achieved by directly manipulating the bitstream using a layered framework. Experimental results on a case study have shown that benchmark circuit evolution from an unseeded initial population, as well as a complete recovery of a stuck-at fault is achievable using this platform. An average of 0.47μs is required to perform the genetic mutation, 4.2μs to perform the single point conventional crossover, 3.1μs to perform Partial Match Crossover (PMX) as well as Order Crossover (OX), 2.8μs to perform Cycle Crossover (CX), and 1.1ms for one input pattern intrinsic evaluation. These represent a performance advantage of three orders of magnitude over the JBITS software framework and more than seven orders of magnitude over the Xilinx design tool driven flow for realizing intrinsic genetic operators on Xilinx Virtex Family devices.