Intra mode power saving methodology for CGRA-based reconfigurable processor architectures

Abstract

Reconfigurable processors (RP) such as Samsung Reconfigurable Processor (SRP) are best suited for wide range of embedded DSP application domains such as image, audio, video and vision processing. It provides great flexibility of hardware reconfigurability through software solution which provides high-performance computing with low-energy and fast time-to-market. Power consumption of the processor architecture is one of the important considerations for mobile DSP solutions. However, the performance critical code sections of applications mapped to RPs may not utilize all minicores (group of functional units, local register files and their connections) due to low ILP (Instruction Level Parallelism) even after exploring software pipelining by the compiler. The unused minicores can consume considerable amount of power (including power leakage) from configuration memory banks, functional units, local register files, and also from central register files of RP architectures. There are approaches in RP to power-gate the minicores when we switch from VLIW (Very Large Instruction Word) mode of RP operation to CGRA (Coarse Grained Reconfigurable Array) mode (inter-mode power-gating exploration). In this paper, we propose a novel programmer directive based power-gating technique for RP which explores unused resources during VLIW and CGRA mode of execution (intra-mode power-gating). Our approach has shown up to 33% power savings in the SRP CGRA mode and up to 56% power savings in SRP VLIW mode, with additional power-gating circuits that contribute to <1% increase in die area.