Abstract
This study investigates the inter-tier coupling, for a Back-Side Illuminated (BSI) 4-Transistor (4T) pixel with its diode and Transfer Gate on the bottom tier and the rest of its circuitry on the top tier of a 3D Sequential Integration (3DSI) process. Variations due to coupling are compared with variations due to temperature, showing that both effects may result in a readout error of the same order of magnitude for the top-tier readout circuit. Nevertheless, we demonstrate that in a typical rolling readout, the sequence of the pixel control signals makes the coupling effect nearly negligible. As a result, we suggest that the fabrication of an inter-tier ground plane for electrical isolation is not strictly necessary for Monolithic 3D pixels when the readout top tier is directly stacked on the photodiode bottom tier.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
