Abstract
Dividing a large-scale design into parts for hardware prototyping and emulation is very important for integrated circuit design flow. In this paper, we present a suite of algorithms to solve the partitioning problem in general field programmable gate arrays (FPGAs) prototyping and hardware emulation. Our k-way hypergraph partitioner is based on a multi-level framework and its performance is similar to the well-known partitioners hMetis (Karypis et al., 1999) and KaHyPar (Akhremtsev et al., 2017). Based on this framework, we take up some algorithms which solve partitioning problems with varying objectives and constraints extracted from logic emulation scenarios. These objectives and constraints take FPGA resources, interconnection resources, flip-flops, and clock domains into account, which are all important factors in FPGA prototyping and hardware emulation. We test our algorithms using ISPD98 benchmarks and several industry cases. The experimental results show that our algorithms are efficient and effective in solving different partitioning problems.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.