Abstract
This paper proposes a method providing efficient test compression for delay fault testing using enhanced scan design. In the proposed method, the initial and transition vectors of test data are interleaved before test compression using statistical coding. This paper also shows test architecture for delay fault testing using the proposed method. The proposed method is experimentally evaluated from the viewpoint of compression rates. For robust testable path delay fault testing on 11 out of 23 ISCA589 benchmark circuits, the combination of Huffman coding and the proposed method provides higher compression rates than Huffman coding without the proposed method, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC)
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