Interleaving: an additional topological compaction technique for Weinberger array generation

Abstract

A program for the generation of Weinberger arrays from Boolean expressions is described. To minimize the area required to implement a function, an array may be folded. A new algorithm is presented that further minimizes the area by causing transistors from adjacent rows to be interleaved. The interleaving process allows area reductions beyond the folding limit, and it can be included in the optimization process either as an additional task after folding, as in the paper, or, alternatively, during folding.