Interior area removal method for p y r a m i d

Abstract

In previous years, pyramid, a hierarchical rule-based scheme for proximity effect correction in electron-beam lithography was presented. pyramid has produced good experimental results for large circuit patterns (up to 80 μm × 80 μm) with a minimum feature size of 0.1 μm in 200 and 500 nm poly(methylmethacrylate) (PMMA) on silicon. Although the circuits used to test pyramid in the past have contained a rapidly varying pattern density, they did not contain very large features (e.g., 10 μm × 10 μm) next to small (0.1 μm) elements. The previous method for performing circuit correction (edge adjustment) has been found to be inadequate when correcting such occurrences. In order to overcome this problem, a new correction technique has been added to the overall pyramid hierarchy. Previously, pyramid performed its correction by adjusting only the locations of the edges of circuit elements. This new correction technique expands upon the previous edge adjustment method by allowing pyramid to remove area from circuit elements not only from the edges, but also from the interior as well. This interior area removal technique substantially improves the correction in cases when small circuit elements are placed near very large features. This article motivates the use of interior area removal both through simulation and experimental results. Experimental results indicating the usefulness of interior area removal are provided.