Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS

Abstract

This work proposes a DSP technique to mitigate the interference-induced spurious tones coupled to the digitally controlled oscillator (DCO) of a digital phase locked loop (DPLL). We leverage the digitized phase information at the time-to-digital converter (TDC) output, and formulate an adaptive algorithm to identify the interference pattern from any electrical or magnetic coupling path, and inject the cancellation signal accordingly. The proposed algorithm also keeps track of the magnitude and phase variation in the background. We experiment with the algorithm in a 65nm 3–5 GHz DPLL prototype and observe 10 ∼ 30 dB spur reduction from different coupling paths to the DCO over various interference frequencies. Additionally, the prototype measures reference spur of <−110dBc and phase noise of − 129dBc/Hz at 3MHz offset frequency.