Interfacing, often a performance bottleneck between ATE and device under test

Abstract

Problems in adapting the interface of VLSI test systems to the device under test (DUT) are reviewed. The focus is on efforts to avoid the electrical degradation of the DUT, especially with increasing operating speeds and increasing pincounts. The channel cards or pin electronics of the automatic test equipment (ATE) have to be flexible and as close to the DUT as possible, and the electromechanical interface, known as the device interface board (DIB) or loadboard, has to be of high quality. For an ATE of given and known performance, the final results therefore very often depend on the performance of such DIBs. Variations of test results caused by wiring on the DIB may decrease the total yield or let the device get binned into a lower category. In the production test areas, there is an inherent tendency to save costs and hence use a so-called 'mother-daughter' board concept for DIBs. For slower NMOS devices and generally for devices with uncritical timing, this concept is acceptable. However, for modern CMOS devices with fast switching outputs, the insertion of pogo pins in the transmission line and the availability of fewer pins for the ground connections could severely degrade the performance of testing. >