Abstract
Ge Metal-Oxide-Semiconductor (MOS) capacitor with HfTiON/ZrLaON stacked gate dielectric and fluorine-plasma treatment is fabricated, and its interfacial and electrical properties are compared with its counterparts without the ZrLaON passivation layer or the fluorine-plasma treatment. Experimental results show that the sample exhibits excellent performances: low interface-state density (3.7×1011 cm−2eV−1), small flatband voltage (0.21 V), good capacitance-voltage behavior, small frequency dispersion and low gate leakage current (4.41×10−5 A/cm2 at Vg = Vfb + 1V). These should be attributed to the suppressed growth of unstable Ge oxides on the Ge surface during gate-dielectric annealing by the ZrLaON interlayer and fluorine incorporation, thus greatly reducing the defective states at/near the ZrLaON/Ge interface and improving the electrical properties of the device.
Highlights
Ge-based MOSFET with high-k gate dielectric has been widely investigated due to its higher carrier mobility [1, 2] and easier integration of Ge on Si than III-V semiconductors on Si
The post-stressing increase of the leakage current is smallest for the ZrLaON+F sample, which can be associated with less generation of the interface and near-interface traps during the constant-voltage stressing due to very little GeOx at/near the ZrLaON /Ge interface [28], as confirmed by X-ray photoelectron spectroscopy (XPS) result below
The content of GeON is higher for the ZrLaON+F sample (2.6% from the GeON/Ge3d peakarea ratio) than the ZrLaON sample (1.1%). These results indicate that fluorine incorporation can further reduce the oxide traps, beneficial for formation of GeON and block the inter-diffusion of elements near the interface, resulting in the best interface quality and electrical properties, as shown for the ZrLaON+F sample above
Summary
Ge-based MOSFET with high-k gate dielectric has been widely investigated due to its higher carrier mobility [1, 2] and easier integration of Ge on Si than III-V semiconductors on Si. In this work, the Ge MOS device with ZrLaON as passivation interlayer and HfTiON as high-k layer is proposed and prepared.
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