Abstract

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si-SiO/sub 2/ interface by hole emission from interface traps to the valence band and electron emission from interface traps to the conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In experiment, a 0.5 /spl mu/m n-MOSFET was subject to hot carrier stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, is responsible for the leakage current at a large drain-to-gate bias (V/sub dg/) The lateral field plays a dominant role in the two-step tunneling process. As V/sub dg/ decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V/sub dg/, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron hole pairs through traps is dominant. >

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.