Interface Trap Density Estimation in FinFETs Using the Method in the Subthreshold Regime

Abstract

In this paper, we show that the subthreshold current–voltage characteristic can be used for estimating the interface trap density as a function of the energy in fully depleted symmetric metal-oxide-semiconductor devices with a minimum amount of modeling. The method is analyzed using TCAD simulations, and illustrated with the measurements on n-type silicon-on-insulator FinFETs. The results indicate that the trap density can be extracted between $\sim 0.65$ and 0.90 eV. This range is limited by resolution issues at the lowest current levels, and by the transition from subthreshold to saturation behavior at the high current levels.