Interface state generation of Al2O3/InGaAs MOS structures by electrical stress

Abstract

Impact of electrical stress on Atomic Layer Deposition (ALD) Al2O3/InGaAs MOS interface properties is experimentally studied in terms of the polarity dependence. It is found in Al2O3/InGaAs MOS structures that the negative bias stress generates larger Dit than the positive bias stress under the constant current or even constant oxide voltage condition. Also, the negative bias stress causes hole trapping, while the positive bias stress leads to electron trapping. A physical mechanism responsible for these phenomena is discussed. Several hole-driven interface state generation models are discussed under the experimental observation of the correlation of higher hole trapping and Dit generation under the gate negative stress.