Interface state density in the interelectrode region of overlapping polycrystalline silicon gates

Abstract

Constant capacitance deep-level transient spectroscopy was applied to analyze the interface state density in the interelectrode region of metal-oxide-semiconductor (MOS) structures having over-lapping polycrystalline silicon gates. A dual-gate structure fabricated on an integrated circuit chip by the double polycrystalline silicon technology was used to vary the extent of the space-charge region in the boundary. The interface state density D*it per boundary length was determined in MOS structures on p-type silicon to D*it =3×106 cm−1 eV−1 at the energy EV +0.99 eV. The interface state density Dit per unit area increases from a value Dit ≊109 cm−2 eV−1 under the bulk gate to Dit ≊1011 cm−2 eV−1 in the boundary region.