Interface oxide trap characterisation in germanium-on-insulator 0.12 μm PMOS transistors by drain current noise measurements

Abstract

This paper presents an experimental analysis of the noise measurements performed in germanium on insulator (GeOI) 0.12 mum PMOS transistors. The front gate stack is composed of a SiO2/HfO2 material with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front gate and back gate oxides/Ge interfaces are characterized. The slow oxide trap densities of the two interfaces are extracted. The values obtained for the front gate oxide are N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fn</sub> ) = 1.2 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> and are comparable to values for nitrided oxides on Si bulk. The extracted values for slow oxide trap densities of the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ge interface are between 6 and 8 1017 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> and are close to those of state of art buried oxide SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interfaces. These results are of importance for the future development of GeOI technologies.