Interface optimization of La-based gate dielectric for molybdenum disulfide field-effect transistors

Abstract

Two-dimensional (2D) layered materials such as graphene, transition metal dichalcogenides are considered as the promising candidates for new generation electronics and optoelectronics, owing to their unique physical properties and abundant design freedom. However, the problem of heterogeneous integration of two-dimensional materials with gate dielectric materials has not been solved, especially the problem of interface qualities, which limits the development of two-dimensional electronics. Herein, we demonstrate the feasibility of interface optimization through post-deposition annealing process. The proposed La-based oxide MoS2 transistor offers high mobility of 60 cm2/V·s, increased by 136% up to ∼ 50uA/um and low interface trap density after post-deposition annealing treatment. The detailed research results show that N2 atmosphere annealing treatment can not only promote the composition of LaAlO3, but also suppress the Coulomb scattering generated from interface state charge. All these results provide an enhanced fabrication scheme for heterogeneous integration with the optimized interface and offer reference for high-reliability manufacturing of low-power two-dimensional electronic devices.