Interface controlled thermal resistances\xa0of ultra-thin chalcogenide-based phase change memory devices

Kiumars Aryana,James M Howe,Patrick E Hopkins,Saikat Mukhopadhyay,John T Gaskins,Ashutosh Giri,Zhaoqiang Bai,John C Read,Eric R Hoglund,Derek A Stewart,Michael K Grobis,Joyeeta Nag,David H Olson

doi:10.1038/s41467-020-20661-8

Abstract

Phase change memory (PCM) is a rapidly growing technology that not only offers advancements in storage-class memories but also enables in-memory data processing to overcome the von Neumann bottleneck. In PCMs, data storage is driven by thermal excitation. However, there is limited research regarding PCM thermal properties at length scales close to the memory cell dimensions. Our work presents a new paradigm to manage thermal transport in memory cells by manipulating the interfacial thermal resistance between the phase change unit and the electrodes without incorporating additional insulating layers. Experimental measurements show a substantial change in interfacial thermal resistance as GST transitions from cubic to hexagonal crystal structure, resulting in a factor of 4 reduction in the effective thermal conductivity. Simulations reveal that interfacial resistance between PCM and its adjacent layer can reduce the reset current for 20 and 120 nm diameter devices by up to ~ 40% and ~ 50%, respectively. These thermal insights present a new opportunity to reduce power and operating currents in PCMs.

Highlights

Phase change memory (PCM) is a rapidly growing technology that offers advancements in storage-class memories and enables in-memory data processing to overcome the von Neumann bottleneck
Our work focuses on identifying the critical parameters that influence thermal transport as the length scale of the phase change unit approaches that of energy carriers’ mean free paths
The results presented here are for commonly used materials in PCMs such as GST and W, we demonstrate that, through manipulation of the interfacial resistance between the phase change unit and the adjacent layer, the predicted reset current can be reduced by up to 40% and 50% for devices with lateral size of 20 and 120 nm in diameters, respectively

Summary

Introduction

Phase change memory (PCM) is a rapidly growing technology that offers advancements in storage-class memories and enables in-memory data processing to overcome the von Neumann bottleneck. Simulations reveal that interfacial resistance between PCM and its adjacent layer can reduce the reset current for 20 and 120 nm diameter devices by up to ~ 40% and ~ 50%, respectively These thermal insights present a new opportunity to reduce power and operating currents in PCMs. The growing demands for higher capacity memory devices and burgeoning data-intensive applications, such as artificial intelligence, have intensified efforts to beat the von Neumann computing bottleneck that separates processing from the storage unit. As Xiong et al.[16] demonstrated, in order to decrease power consumption and further the economic benefits of PCM memory devices, the thickness of GST layers should be on the order of 10 nm In this respect, Kim et al.[17] devised an operational PCM device with cell dimensions as small as 7.5 nm × 17 nm. Our work uses this knowledge of carrier dynamics to experimentally identify an optimal thickness of phase change material based on a balance of thermal conductivity and crystallographic-phase-dependent thermal boundary conductances (TBCs) in order to improve memory device performance

Methods

Results

Conclusion