Abstract
This paper introduces a design method for SOPC (System on Programmable Chip) based on embedded Nios II soft-core processor. The interface between the soft-core processor Nios II and the TDC module is given, and the initial programming technique and Nios II application programme is explained at the same time.
Highlights
Email: zjw0128 @tom.com Abstract This paper introduces a design method for SOPC (System on Programmable Chip) based on embedded Nios II soft-core processor
Dedicated instructions for computing 64-bit and 128-bit products of multiplication Floating-point instructions for single-precision floating-point operations Single-instruction barrel shifter Access to a variety of on-chip peripherals, and interfaces to off-chip memories and peripherals Hardware-assisted debug module enabling processor start, stop, step and trace under integrated development environment (IDE)control Software development environment based on the GNU C/C++ tool chain and Eclipse IDE
As NiosII soft-core processor design can use a lot of nuclear molding IP, and Nios II processors can link the external memory, LCD display, ethernet controller and USB, peripherals for the coordination and sharing of data
Summary
TDC - GP1 chip is a dual-channel Universal time-to-digital converter chip, with the largest range of 200ms and accuracy of 125 ps. Chip supports two working range and kinds of work patterns and it has flexible work practices. TDC-GP1 use 44 pin TQFP package with TDC measurement unit, 16-ALU, RLC measurement unit and eight processor interface modules. The pin names and functions are listed in Table 1(Acam, 2001)
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