Interface Analysis of Embedded Chip Resistor Device Package and Its Effect on Drop Shock Reliability

Abstract

In this study, the drop reliability of an embedded passive package is investigated under JESD22-B111 condition. Chip resistors were buried in a PCB board, and it was electrically interconnected by electroless and electrolytic copper plating on a tin pad of a chip resistor without intermetallic phase. However tin, nickel, and copper formed a complex intermetallic phase, such as (Cu, Ni)6Sn5, (Cu, Ni)3Sn, and (Ni, Cu)3Sn2, at the via interface and via wall after reflow and aging. Since the amount of the tin layer was small compared with the solder joint, excessive intermetallic layer growth was not observed during thermal aging. Drop failures are always initiated at the IMC interface, and as aging time increases Cu-Sn-Ni IMC phases are transformed continuously due to Cu diffusion. We studied the intermetallic formation of the Cu via interface and simulated the stress distribution of drop shock by using material properties and board structure of embedded passive boards. The drop simulation was conducted according to the JEDEC standard. It was revealed that the crack starting point related to failure fracture changed due to intermetallic phase transformation along the via interface, and the position where failure occurs experimentally agrees well with our simulation results.