Interconnection via technology and wafer level package for crystal unit device

Abstract

Most important technology for developing of wafer level packaging is studied in this paper. That is the process of drilling the via hole that are needed filling of conductive material for electrical connection or non-conductive material for reliability. Several kinds of drilling and filling methods of via holes for the interconnection were studied. The via formation for interconnection is based on smaller and lower cost package process. However, glass wafer which is substrate material of wafer level package for crystal unit device is difficult to make via by using novel method. The structure of wafer level crystal unit package for low cost and high performance is designed and optimized. The glass and Si wafer for package substrate and lid is chosen and considered as the structure for its mechanical and thermal strength and effective process of mass production. The interconnection via is formed through glass wafer by using sand blasting or laser drilling and Cu electro-plating method that enable the connection of the signal electrode on the quartz blank. The interconnection via process for wafer level crystal unit package with 2.0×1.6×0.45 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> size and results of electrical performance is evaluated.