Interconnect simulation in a fast timing simulator ILLIADS-I

Abstract

This paper presents a new technique to simulate RLC/RC interconnects and driving nonlinear circuits with high computational efficiency. We introduce ILLIADS-I, a fast transistor-level timing simulator for MOS circuits driving RLC/RC interconnects. The RLC/RC interconnect networks are reduced to an appropriate model and then simulated in the timing simulator as a modified generic circuit primitive. The accuracy and speed have been demonstrated for a number of circuits for various loads and input waveforms. Experimental results show ILLIADS-I is both accurate and fast. The speed advantage Is shown to increase with the circuit size for multilevel interconnect networks with nonlinear driver and load circuits.