Abstract
Transistor and interconnect pitch scaling has been used successfully for greater than 40 years to drive significant density and performance benefits in integrated circuits. Transistor performance has continued to improve due to pitch scaling combined with other process enhancements. Interconnects represent a much larger portion of the overall delay and cost of integrated circuits today than in the past. This paper reviews the relative comparison of interconnect and transistor scaling and key interconnect scaling challenges, and it highlights the transistor/interconnect co-optimization that is needed to create high performance and high yielding interconnects sufficient for today's ultra-large scale integration (ULSI) needs, and reviews future trends.
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