Abstract
In previous research interconnection was optimised when the module allocation for the operations and the register allocation for the variables already had been done. However, both the amount of multiplexing and interconnect are crucial factors to both the delay and the area of a circuit. In this paper it is shown that when variables are grouped into register files and operations are assigned to modules to minimise the interconnections, significant savings (20%) can be obtained in the number of local interconnections and the amount of global interconnect on the expense of only slightly more register area. This can be enhanced by splitting read and write phases of registers and even more by introducing serial (re-) write operations for the same value. The variable grouping is based on edge colouring algorithms that provide a sharp upper bound on the number of colours needed. >
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