Interconnect fabrication processes and the development of low-cost wiring for CMOS products

Abstract

As the cost and performance of integrated circuit (IC) interconnections, or “interconnects,” become increasingly important to the development and manufacturing of successful advanced IC products, so also do underlying metallization and patterning processes. In particular, the goals of achieving product design specifications, low development cost (high and early yield), low manufacturing cost, and portability across products can only result from applying robust unit processes that combine to form integrable and scalable process modules. In this paper, we review the interconnect fabrication processes used to form currently manufactured IBM CMOS products, and describe the materials and process integration issues that motivated their selection. In addition, we identify factors which may inhibit application of the fabrication processes to future products having smaller dimensions. The review suggests that large improvements in cost and scalability can be achieved by forming dual-damascene monolithic studs/wires. Previously, the dual-damascene approach was not generally applicable because of the lack of suitable metal deposition techniques for filling high-aspect-ratio features with highly conductive metal. However, recent advances may provide that capability both for near-term applications using Al-based wiring, and also for future applications using more extendible Cu-based wiring.