Interconnect Design and Thermal Stress/Strain Analysis of Flip Chip Packaging

Abstract

As the interconnection density of electronic packaging continues to increase, the fatigueinduced solder joint failure of surface mounted electronic devices become one of the most critical reliability issues in electronic packaging industry. Especially, prediction of the shape of solder joint is a major event in the development of electronic packaging for its practical engineering application. In conventional electronic packages, the geometrical dimensions of solder balls and solder pads of the package are the same. In this research, a hybrid method combined with analytical and energybased methods is utilized to predict force-balanced heights and geometry profiles of solder balls under various solder volume and pad dimensions as well as their relative location during the reflow process. Next, a non-linear finite element analysis is adopted to investigate the stress/strain behavior of solder balls in flip chip package. The results reveal that as the flip chip package contains larger solder balls located at the corner area underneath the chip, the maximum equivalent plastic strain/stress is evidently reduced and the reliability cycles under thermal loading are enhanced. Furthermore, the results presented in this research can be used as a design guideline for area array interconnections.