Abstract
As integrated circuit process technology is changing into the ultra deep submicron era, the complex interconnection topology and metal resistance shielding effects problem is very serious, resulting in very stiff interconnection structure. As inaccurate delay on stiff interconnect sinks creates a situation where decisions on when to evaluate by statistical static time analysis (SSTA) are not cluster distribution, we cannot roughly classify the interconnect into near-end, middle-end, and far-end. Although several delay metrics have been proposed, they are inefficient and difficult to implement. Hence, we propose a new delay and slew metric for interconnect based on Extreme Value Distribution only using the first two moments. Our metrics are efficient, easy to implement, and can precisely label inaccurate sinks and efficiently calibrate them; the overall standard deviation and error mean are smaller than in previous works.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.