Interactive VLSI Chip Floor Design Using Color Graphics

Abstract

In a hierarchical VLSI design, the block-level layout design is called ‘chip floor plan’. This paper presents a semi-automatic VLSI chip floor plan program CHAMP, which utilizes a color graphic terminal to the fullest. It has an automatic initial placement and semi-automatic block packing procedures. In the chip floor plan problem, because of the variety of block sizes and shapes, it is very difficult to minimize the chip area by only an automatic process using a computer. Consequently, in most cases, the optimum solution is not obtained without the help of a human designer. To facilitate the manual optimization process, CHAMP is provided with a set of interactive commands using a color graphic terminal. In this paper, chip floor plan program CHAMP is described, in which its interactive facilities are emphasized, and the application results are discussed.