Integration of UML and VHDL-AMS for analogue system modelling

Abstract

Abstract. This paper details a new object-oriented methodology that permits a unified modelling language (UML) behavioural representation of analogue circuits at system level. The proposed method demonstrates a novel approach to the problem of behavioural representation of an analogue topology, by constructing a consistent set of rules for automated mapping of the UML model to a VHDL-AMS specification. The VHDL-AMS specification enables behavioural simulation of the UML model and the methodology is validated using an analogue subsystem level application.