Integration of Passive Components into 3D PoP Fan-Out Packages

Abstract

Fan-Out Wafer Level Packages provide a flexible assembly platform for single die, multi-chip, and 3D structures in a minimal form factor. As a result, the FO-WLP has gained rapid acceptance as a competitive package in the fast growing market of mobile devices. The eWLB version of FO-WLP has achieved the greatest commercial success, with millions of units already assembled and shipped in mobile phones. Although multi-chip structures have been discussed previously, one capability of the technology that has not received wide attention is the incorporation of passive devices into the packages. There are two common implementations of 3D packaging with the FO-WLP technology. The first is fan-out packages with one sided redistribution layers (RDL) using laser drilled vias to enable the direct mount of top packages. The second is two sided packages with through-mold vias that enable RDL on both the top and the bottom of the package. Using multichip embedding technology, it is possible to embed discrete components such as capacitors, resistors, or inductors into the body of the fan-out package in very close proximity to the active device. This close proximity to the active device combined with Cu RDL routing provides exceptional performance for decoupling capacitors and other passive devices. In a two sided RDL implementation, routing can be provided on the top of the package to enable integrated inductors and pads for direct mounting of additional passive components. This two sided implementation can reduce the combined board footprint of active devices and their required passives through the use of 3D integration. This presentation will discuss the various implementations of embedded passives in the 3D FO-WLP and the form factors that can be achieved with this solution.