Integration of Low Resistive CVD-W Interconnects for sub-50nm FEOL application

Abstract

Low resistive tungsten (LRW) interconnects using CVD-W films deposited on B <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</inf> -reduced W nucleation layers have been successfully developed for FEOL application of sub-50nm dynamic random access memory (DRAM). LRW poly-metal gate showed excellent gate oxide integrity, low sheet resistance, low parasitic capacitance, and excellent transistor performances such as ring-oscillator delay comparable to PVD-W based poly-metal gate. In the bit line application, as the feature size was decreased, the contact resistance and sheet resistance of LRW bit line were decreased drastically compared to conventional CVD-W process. However, the properties of junction leakage current and saturation drain current (Idsat) of NMOS transistor were degraded due to the penetration of boron into the junction. In order to depress the junction degradation, the improvement of barrier properties of glue-layer and optimization of LRW process were suggested.