Integration of high-voltage NMOS devices into a sub micron BiCMOS process using simple structural changes

Abstract

This paper reports on the integration of high-voltage NMOS devices into a low-voltage 0.8 /spl mu/m BiCMOS process using simple structural changes. A high-voltage device structure, fully compatible with a standard process, is proposed. Two-dimensional process and device simulations are used to study the effect of layout parameters on the performance of the device. While short gate lengths are feasible using advanced submicron processing, 1.5 /spl mu/m was found to be the minimum gate length without channel punchthrough. Depending on the drift region length (3-16 /spl mu/m), breakdown voltages and specific on-resistances in the ranges of 70-124 V and 1.5-19 m/spl Omega/cm/sup 2/ were respectively obtained on experimental test devices with a gate length of 1.5 /spl mu/m. Because of their full compatibility with the process, these high-voltage devices have the same threshold voltage (0.8 V) as their low-voltage counterparts. >