Integration of Carbon Nanotube Interconnects for Full Compatibility with Semiconductor Technologies

Abstract

We report the latest works on via interconnects of future memory or LSI devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. MWCNTs are grown vertically in 80 nm via holes using plasma-enhanced chemical vapor deposition. The carbon nanotube (CNT) via interconnects are integrated into an 8-inch Si wafer in full compatibility with conventional semiconductor processes. We have used buried catalyst method for the catalyst layer deposition, two-step etch method for achieving via etch stop on the thin catalyst layer (ca. 3 nm), and the chemical mechanical polishing (CMP) process for cutting CNT. The two-step etch method is composed of two consecutive etch steps: the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to relieve the damage of the catalyst layer. After a full integration, a resistance of 293 ∼ 493 Ω and a CNT density of about 4 × 1011/cm2 have been achieved for the 80 nm via. These results show that the 2-step etch scheme is a promising candidate for the realization of CNT interconnects in conventional semiconductor devices.