Abstract
We demonstrate the hybrid integration of an O-band vertical-cavity surface-emitting laser (VCSEL) onto a silicon photonic chip using a grating coupler that is optimized to simultaneously provide feedback to maintain the single emission polarization and efficient in-plane coupling. The grating coupler was fabricated on silicon-on-insulator using a standard silicon photonics foundry process, and integrated with a commercially available VCSEL. A transparent VCSEL submount was fabricated with femtosecond laser templating and chemical etching to simplify the passive and active alignment steps. A record-high VCSEL-to-chip coupling efficiency of -5 dB was obtained at a bias current of 2.5 mA. The slope efficiency and output power are competitive with microcavity hybrid silicon lasers. The results show the feasibility of VCSELs as low threshold current on-chip sources for silicon photonics.
Highlights
Silicon photonics (SiP) has the potential to satisfy the cost, volume, and integration requirements of photonic integrated circuits (PIC) for a wide range of applications including optical communications, computing, and sensing [1]
We report the hybrid integration of a commercial vertical-cavity surfaceemitting laser (VCSEL) at a wavelength near 1330 nm with a foundry-fabricated SiP chip where a vertical grating coupler (VGC) provided external optical feedback (OF) to maintain the VCSEL polarization state
The VCSEL output is directed downward to the VGC, which couples a part of the optical power to an in-plane Si waveguide
Summary
Silicon photonics (SiP) has the potential to satisfy the cost, volume, and integration requirements of photonic integrated circuits (PIC) for a wide range of applications including optical communications, computing, and sensing [1]. One hybrid integration approach is to bond III-V gain material onto SiP and design hybrid III-V-Si waveguide modes that can be optically amplified [4,5,6]. The alignment precision required between the III-V device and features in the SiP is relaxed and the bonding can be done at the wafer-scale. The second approach is to mount pre-processed laser dies onto SiP chips using assemblies, flip-chip bonding, and wire bonding [7, 8]. This may require larger die areas and more manufacturing time, it has the major advantage that the lasers can be burnt-in and pretested prior to co-packaging with SiP
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