Abstract
In the latest edition of the International Technology Roadmap for Semiconductors (ITRS), the predicted time for the introduction of porous ultra low- k materials with a dielectric constant of 2.2 has slipped significantly against earlier predictions. This is largely due to greater-than-expected problems with the integration of these fragile materials, which generally exhibit weak mechanical properties and low resistance against chemical attack, requiring great care during the integration process. This paper discusses some of the challenges encountered and improvements made at International Sematech and elsewhere regarding the integration of spin-on porous ultra low- k dielectrics into a copper dual damascene process.
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