Abstract
In this paper, we report on the integration of a spin-on low- k material (ENSEMBLE™ PMD) at the pre-metal dielectric (PMD) level of CMOS logic circuits processed using 0.13 μm node modules. Modifications to the conventional integration flow, where high-density plasma phospho-silicate glass (HDP-PSG) is used as PMD material, are made to the planarization steps and etch/strip sequence. Although on stand-alone transistors there is no measurable impact of the lower capacitance, a significant decrease of the switching delay of invertors in ring oscillator structures loaded with a metal/poly plate capacitor is observed. This demonstrates the possible positive impact of low- k on the performance of circuits of which the lowest level of back-end routing has a large overlap to underlying silicided areas.
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