Integrated Stateflow-based simulation modelling and testability evaluation for electronic built-in-test (BIT) systems

Abstract

The simulation modelling for built-in test (BIT) system is an important approach to analyse the testability and evaluate the BIT performance. However, existing simulation modelling methods cannot satisfy the simulation requirements of abundant testability design factors, especially for the fault and interference injection and the test logic of BIT. Therefore, this paper proposes an integrated modelling and simulation method for BIT system based on Stateflow. This simulation modelling method has three highlights. 1) this method can dynamically realise the fault transmission and BIT monitoring processes under test. 2) this method can generate diagnostic knowledge through the fault injection function. 3) this method can calculate BIT performance metrics, especially the false alarm probability to realise more comprehensive testability evaluation. This paper firstly presents the BIT detection, isolation, and false alarm reduction logics and model formulation. Then the testability metrics and d-matrix calculation models are presented. Finally, the proposed method is applied in an example of an electronic secondary power conversion board. The testability metrics are reported by the simulation model, which comply with the real hardware analysis and experiment.