Abstract
The paper presents a protection technique for CMOS ASIC designs, based on the integrated Single Event Latchup (SEL) protection. Triple or double modular redundancy, together with integrated SEL protection switches (SPS) make the base for the fault-tolerant ASICs, able to operate in space environment. The presented approach represents a cheap solution, based on standard non-radiation hardened process. The SPS has been designed, characterized and verified in both standard and radiation environment. The proposed protection technique requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. The concept has been verified on silicon.
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