Abstract
One long-standing goal in the emerging neuromorphic field is to create a reliable neural network hardware implementation that has low energy consumption, while providing massively parallel computation. Although diverse oxide-based devices have made significant progress as artificial synaptic and neuronal components, these devices still need further optimization regarding linearity, symmetry, and stability. Here, we present a proof-of-concept experiment for integrated neuromorphic computing networks by utilizing spintronics-based synapse (spin-S) and neuron (spin-N) devices, along with linear and symmetric weight responses for spin-S using a stripe domain and activation functions for spin-N. An integrated neural network of electrically connected spin-S and spin-N successfully proves the integration function for a simple pattern classification task. We simulate a spin-N network using the extracted device characteristics and demonstrate a high classification accuracy (over 93%) for the spin-S and spin-N optimization without the assistance of additional software or circuits required in previous reports. These experimental studies provide a new path toward establishing more compact and efficient neural network systems with optimized multifunctional spintronic devices.
Highlights
1234567890():,; 1234567890():,; 1234567890():,; 1234567890():,; Introduction Advances in hardware technologies have resulted in hardware implementations of numerous neural network algorithms, including deep neural networks and convolutional neural networks, that use a feasible amount of computing resources
Developing neuron components that can be monolithically integrated at a simple device level with the existing weight device crossbar array in a compatible fabrication process are necessary for widespread use in hardware-based neural networks
The accuracy remained >93% even for the full hardware combination. These results indicate that the proposed spin-S and spin-N devices provide a novel solution for building a complete neuromorphic computing hardware implementation, while previously reported artificial synapse devices require a software-assisted rectified linear unit (ReLU) activation function to play a neuron role
Summary
Advances in hardware technologies have resulted in hardware implementations of numerous neural network algorithms, including deep neural networks and convolutional neural networks, that use a feasible amount of computing resources. Spintronics-based devices, such as those employing current-induced domain wall (DW) motion, have attracted considerable interest as basic building blocks for advanced neuromorphic component deployments These devices offer low-power consumption, and highly stable and reproducible operation[15,16,17,18,19,20], according to the experimentally well-established model[21,22]. By tuning the device operation principles, we test a DW-based neuron (spin-N) in the same device geometry that functions as a sigmoidal activation function and has a voltage output signal Together, these findings provide a new crossbar array configuration that employs voltage output (Hall voltage) weights and acts as a DNN accelerator. We propose the concept of how the voltage output signal of the spin-Ss can operate the spin-N at an array level, along with an experimental demonstration
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
