Abstract
Integrated injection logic (I/SUP 2/L) or merged transistor logic (MTL) incorporating lateral p-n-p transistors as current sources and multicollector n-p-n transistors as invertors, are discussed. Speed-power products of 0.13 pJ per gate have been measured in a five-stage closed-loop invertor chain, and packing densities of 400 gates/mm/SUP 2/ have been achieved. A layout comparison with MOS logic is presented. A possible way of producing faster circuits is proposed.
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